While digital waveform averaging is effective at reducing uncorrelated error, it cannot distinguish the common waveform of interest from correlated errors, i.e., noise and distortion that is common across all waveforms. One source of correlated error can arise in the digitization process itself because of non-idealities in the sample interleaving process used in high-speed analog-to-digital converters (ADCs). Sample interleaving is a widely used technique to achieve high-sample rate digitization by employing multiple sub-sample rate ADC cores in parallel, but this can result in unwanted correlated errors in the waveform.
This LLNL invention introduces a technique for optimally detuning the ADC and signal clocks while maintaining synchronization between the two to manage correlated errors in waveform processing. This technique maintains synchronization between the two clocks, but with optimal detuning applied the interleaving artifacts are maximally decorrelated across waveforms and thus suppressed with averaging.
Right Image Caption: An illustrative example of waveform averaging over multiple ADC Cores
Current stage of technology development: TRL ☐ 0-2 ☒ 3-5 ☐ 5-9
LLNL has filed for patent protection on this invention.
By maintaining synchronization of the ADC and signal clocks, we can keep the associated benefits of lower trigger jitter during initiation of the waveform signal and ensure consistent sampling points compared to other ADC methods.
Novel high accuracy oscilloscopes, high fidelity signal processing equipment for laser waveform optimization, general high fidelity signal processing in telecommunications equipment.
