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SEM image of a prototype for a neural implant shuttle etched into a non-SOI wafer. The 7:1 (Si:Photoresist) etch selectivity used here allowed for a maximum structure height of 32 μm, with up to 75 steps of 0.4 μm height each. Scale bar 100 μm.

For this method, a Silicon on Insulator (SOI) wafer is used to tailor etch rates and thickness in initial steps of the process.  The simple three step process approach is comprised of grayscale lithography, deep reactive-ion etch (DRIE) and liftoff of the SOI wafer.  The liftoff process is used to dissolve the insulating layer, thus separating sections of the wafer as individual…

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LLNL has developed a new method for increasing lifetime in quantum coherent devices.

LLNL has developed a method of extending device lifetimes by imprinting into the device a shape that excludes specific vibrational modes, otherwise known as a phononic bandgap. Eliminating these modes prevents one of the primary energy loss pathways in these devices. LLNL’s new method enhances the coherence of superconducting circuits by introducing a phononic bandgap around the system’s…

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Sequoia computer panels off

LLNL has developed a new active memory data reorganization engine. In the simplest case, data can be reorganized within the memory system to present a new view of the data. The new view may be a subset or a rearrangement of the original data. As an example, an array of structures might be more efficiently accessed by a CPU as a structure of arrays. Active memory can assemble an alternative…