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SEM image of a prototype for a neural implant shuttle etched into a non-SOI wafer. The 7:1 (Si:Photoresist) etch selectivity used here allowed for a maximum structure height of 32 μm, with up to 75 steps of 0.4 μm height each. Scale bar 100 μm.
3D Silicon Structures Fabricated via Greyscale DRIE

For this method, a Silicon on Insulator (SOI) wafer is used to tailor etch rates and thickness in initial steps of the process.  The simple three step process approach is comprised of grayscale lithography, deep reactive-ion etch (DRIE) and liftoff of the SOI wafer.  The liftoff process is used to dissolve the insulating layer, thus separating sections of the wafer as individual…

Cross Section of the High-Voltage Insulator Joint
High-Voltage Insulator Having Multiple Materials

The approach is to build a high voltage insulator consisting of two materials:  Poly-Ether-Ether-Ketone (“PEEK”) and Machinable Ceramic (“MACOR”).  PEEK has a high stress tolerance but cannot withstand high temperatures, while MACOR has high heat tolerance but is difficult to machine and can be brittle.  MACOR is used for the plasma-facing surface, while PEEK will handle the…

An artist’s concept rendering of a 3.5-meter linear induction accelerator (LIA) with four lines-of-sight toward a patient. The blue elements magnetically focus and direct the LIA’s electron beams.
FLASH Radiotherapy Accelerator

LLNL’s approach is to use their patented Photoconductive Charge Trapping Apparatus (U.S. Patent No. 11,366,401) as the active switch needed to discharge voltage across a vacuum gap in a particle accelerator, like the one described in their other patent (U.S. Patent No.