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CT Scanner Adobe Stock Image

The essence of this invention is a method that couples network architecture using neural implicit representations coupled with a novel parametric motion field to perform limited angle 4D-CT reconstruction of deforming scenes.

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SEM image of a prototype for a neural implant shuttle etched into a non-SOI wafer. The 7:1 (Si:Photoresist) etch selectivity used here allowed for a maximum structure height of 32 μm, with up to 75 steps of 0.4 μm height each. Scale bar 100 μm.

For this method, a Silicon on Insulator (SOI) wafer is used to tailor etch rates and thickness in initial steps of the process.  The simple three step process approach is comprised of grayscale lithography, deep reactive-ion etch (DRIE) and liftoff of the SOI wafer.  The liftoff process is used to dissolve the insulating layer, thus separating sections of the wafer as individual silicon…

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Livermore Tomography Tools  LTT

To solve these challenges using new and existing CT system designs, LLNL has developed an innovative software package for CT data processing and reconstruction. Livermore Tomography Tools (LTT) is a modern integrated software package that includes all aspects of CT modeling, simulation, reconstruction, and analysis algorithms based on the latest research in the field. LTT contains the most…

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Intrinsic Use Control

LLNL's method of equivalent time sampling incorporates an embedded system that generates the pulses used to trigger the external circuit and the data acquisition (DAQ). This removes the external reference clock, allowing the overall system clock rate to change based on the ability of the embedded system. The time delays needed to create the time stepping for equivalent time sampling is done by…