LLNL researchers have invented an ultrafast PCSS to drive a high-power laser diode with arbitrary pulse widths. These devices operate by supplying a high voltage (>10 kV) to one side of the switch. A short pulse of light illuminates the semiconductor, instantly turning it from highly resistive to highly conductive.
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![JFET Device Structure](/sites/default/files/styles/scale_exact_400x400_/public/2023-10/JFET%20device%20structure.png?itok=NRzXbnhk)
LLNL’s novel approach is to use diamond substrates with the desired donor (nitrogen) and acceptor (boron) impurities. In order to optically activate these deep impurities, the invention requires at least one externally or internally integrated light source. The initial exposure to light can set up the desired conduction current, after which the light source could be turned off. Even with…
![Tunneling Diode between two DSRDs](/sites/default/files/styles/scale_exact_400x400_/public/2023-10/TunnelingDiode.png?itok=DfeB26vp)
Instead of producing individual DSRDs and bonding them, Tunnel DSRD's entire stack structure is grown epitaxially on a n- or p-type silicon wafer, resulting in a novel, “monolithic” stacked DSRD. A tunnel diode is essentially a diode with very highly doped p and n regions such that the reverse breakdown voltage is 200 meV or lower.
![thermoelectric cooler (TEC) embedded substrate for cooling of high power devices](/sites/default/files/styles/scale_exact_400x400_/public/2023-06/TEC%20embedded%20substrate.png?itok=vEz7ndQ8)
For cooling a high power device, the novel approach is to use a thermoelectric cooler (TEC)-based embedded substrate with proper selection of the TEC material as an active cooler. The packaging configuration of TEC allows cooling the entire die without the use of a fluid. The process is compatible with the thin film TEC material. Standard semiconductor processes can be used to manufacture…
![SEM image of a prototype for a neural implant shuttle etched into a non-SOI wafer. The 7:1 (Si:Photoresist) etch selectivity used here allowed for a maximum structure height of 32 μm, with up to 75 steps of 0.4 μm height each. Scale bar 100 μm.](/sites/default/files/styles/scale_exact_400x400_/public/2023-05/SEM%20image%20prototype%20neural%20implant%20shuttle.png?itok=fpnfB5Yr)
For this method, a Silicon on Insulator (SOI) wafer is used to tailor etch rates and thickness in initial steps of the process. The simple three step process approach is comprised of grayscale lithography, deep reactive-ion etch (DRIE) and liftoff of the SOI wafer. The liftoff process is used to dissolve the insulating layer, thus separating sections of the wafer as individual silicon…
![Unique LLNL capabilities enable GaN superjunctions](/sites/default/files/styles/scale_exact_400x400_/public/2023-05/GaNSuperjunctions.png?itok=UtrYddDz)
The approach is to use Charge Balance Layers (CBLs) to create a superjunction device in wide bandgap materials. These CBLs enable the device to effectively spread the electric field over 2- or 3-dimensions within a semiconductor voltage sustaining layer instead of 1-dimension, thereby increasing the maximum voltage a device is capable of withstanding. The challenge of using CBLs is the…
![multichannel_pyrometer.jpg multichannel_pyrometer](/sites/default/files/styles/scale_exact_400x400_/public/2019-08/multichannel_pyrometer.jpg?itok=x0sCe_BN)
LLNL researchers have designed and tested performance characteristics for a multichannel pyrometer that works in the NIR from 1200 to 2000 nm. A single datapoint without averaging can be acquired in 14 microseconds (sampling rate of 70,000/s). In conjunction with a diamond anvil cell, the system still works down to about 830K.