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Custom PCB design of a PCSS Laser Diode Driver

LLNL researchers have invented an ultrafast PCSS to drive a high-power laser diode with arbitrary pulse widths.  These devices operate by supplying a high voltage (>10 kV) to one side of the switch.  A short pulse of light illuminates the semiconductor, instantly turning it from highly resistive to highly conductive.

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JFET Device Structure

LLNL’s novel approach is to use diamond substrates with the desired donor (nitrogen) and acceptor (boron) impurities.   In order to optically activate these deep impurities, the invention requires at least one externally or internally integrated light source.  The initial exposure to light can set up the desired conduction current, after which the light source could be turned off.  Even with…

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Tunneling Diode between two DSRDs

Instead of producing individual DSRDs and bonding them, Tunnel DSRD's entire stack structure is grown epitaxially on a n- or p-type silicon wafer, resulting in a novel, “monolithic” stacked DSRD.  A tunnel diode is essentially a diode with very highly doped p and n regions such that the reverse breakdown voltage is 200 meV or lower. 

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thermoelectric cooler (TEC) embedded substrate for cooling of high power devices

For cooling a high power device, the novel approach is to use a thermoelectric cooler (TEC)-based embedded substrate with proper selection of the TEC material as an active cooler.  The packaging configuration of TEC allows cooling the entire die without the use of a fluid.  The process is compatible with the thin film TEC material.  Standard semiconductor processes can be used to manufacture…

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SEM image of a prototype for a neural implant shuttle etched into a non-SOI wafer. The 7:1 (Si:Photoresist) etch selectivity used here allowed for a maximum structure height of 32 μm, with up to 75 steps of 0.4 μm height each. Scale bar 100 μm.

For this method, a Silicon on Insulator (SOI) wafer is used to tailor etch rates and thickness in initial steps of the process.  The simple three step process approach is comprised of grayscale lithography, deep reactive-ion etch (DRIE) and liftoff of the SOI wafer.  The liftoff process is used to dissolve the insulating layer, thus separating sections of the wafer as individual silicon…

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Unique LLNL capabilities enable GaN superjunctions

The approach is to use Charge Balance Layers (CBLs) to create a superjunction device in wide bandgap materials.  These CBLs enable the device to effectively spread the electric field over 2- or 3-dimensions within a semiconductor voltage sustaining layer instead of 1-dimension, thereby increasing the maximum voltage a device is capable of withstanding.  The challenge of using CBLs is the…

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Revolutionary Suppressor Technology

The suppressor has a series of chambers for the propellant to flow through, but unlike all traditional suppressors, the chambers are open, not closed. The propellant is not trapped. It keeps moving. We manage its unimpeded flow through the suppressor. This is the key underlying technology of our suppressor design that enables all the improvements over the 100-year old traditional designs.

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energetic compounds with isotopic labels

Livermore Lab researchers have developed a tunable shaped charge which comprises a cylindrical liner commonly a metal such as copper or molybdenum but almost any solid material can be used and a surround layer of explosive in which the detonation front is constrained to propagate at an angle with respect to the charge axis.  The key to the concept is the ability to deposit a surrounding…

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3d printed structural_energetics

Livermore Lab researchers have developed a method that combines additive manufacturing (AM) with an infill step to render a final component which is energetic. In this case, AM is first used to print a part of the system, and this material can either be inert or energetic on its own. A second material is subsequently added to the structure via a second technique such as casting, melt…