Powder atomic layer deposition process is used to coat nanopowders of host materials (e.g. yttrium aluminum garnet) with optically active neodymium organometal precursor followed by O₂/O₃ RF plasma to convert to a single layer of Nd₂O₃. The process can be repeated to build arbitrarily thick layers with custom doping profiles and followed by post-…

This invention proposes using a pulse laser configured to generate laser pulses and a controller for controlling operation of the pulse laser. The controller is further configured to control the pulse laser to cause the pulse laser to generate at least one of the laser pulses with a spatiotemporally varying laser fluence over a duration of at least one of the laser pulses. The spatiotemporally…

LLNL researchers have invented an ultrafast PCSS to drive a high-power laser diode with arbitrary pulse widths.  These devices operate by supplying a high voltage (>10 kV) to one side of the switch.  A short pulse of light illuminates the semiconductor, instantly turning it from highly resistive to highly conductive. Ultrawide bandgap (UWBG) semiconductors are used to achieve sub-…

LLNL’s novel approach is to use diamond substrates with the desired donor (nitrogen) and acceptor (boron) impurities.   In order to optically activate these deep impurities, the invention requires at least one externally or internally integrated light source.  The initial exposure to light can set up the desired conduction current, after which the light source could be turned…

Instead of producing individual DSRDs and bonding them, Tunnel DSRD's entire stack structure is grown epitaxially on a n- or p-type silicon wafer, resulting in a novel, “monolithic” stacked DSRD.  A tunnel diode is essentially a diode with very highly doped p and n regions such that the reverse breakdown voltage is 200 meV or lower. 

For cooling a high power device, the novel approach is to use a thermoelectric cooler (TEC)-based embedded substrate with proper selection of the TEC material as an active cooler.  The packaging configuration of TEC allows cooling the entire die without the use of a fluid.  The process is compatible with the thin film TEC material.  Standard semiconductor processes can be used…

For this method, a Silicon on Insulator (SOI) wafer is used to tailor etch rates and thickness in initial steps of the process.  The simple three step process approach is comprised of grayscale lithography, deep reactive-ion etch (DRIE) and liftoff of the SOI wafer.  The liftoff process is used to dissolve the insulating layer, thus separating sections of the wafer as individual…

The approach is to use Charge Balance Layers (CBLs) to create a superjunction device in wide bandgap materials.  These CBLs enable the device to effectively spread the electric field over 2- or 3-dimensions within a semiconductor voltage sustaining layer instead of 1-dimension, thereby increasing the maximum voltage a device is capable of withstanding.  The challenge of using CBLs is…

The new LLNL technique works by transiently removing and trapping concrete or rock surface material, so that contaminants are confined in a manner that is easy to isolate and remove. Our studies suggest that 10 m² of surface could be processed per hour. The technique easily scales to more surface/hr.